1. Field of the Invention
The present invention relates to a method for testing a phase-change random access memory (PRAM) device. More particularly, the invention relates to a method for testing a PRAM device which writes set data and reset data simultaneously and thereafter tests the outcome of writing such data.
2. Discussion of Related Art
Semiconductor memory devices are fundamentally characterized by their ability to write (or store) data and read (or retrieve) data. In order to accomplish these operations, every memory cell used to store data in the memory cell array forming the semiconductor memory device must function properly. This presents a significant challenge since contemporary semiconductor devices often include literally billions of individual memory cells. While the number of inoperative memory cells (hereafter referred to as “fail cells”) is very low given the well developed fabrication processes used to manufacture semiconductor memory device, some almost always exist in the memory cell array. It is therefore necessary to identify all of the fail cells in a semiconductor memory device before its use in order to fix or replace each fail cell. Thus, accurate memory cell testing is required to ensure reliable operation of semiconductor memory devices.
During read/write function testing of a semiconductor memory device, each individual memory cell will be determined to be either a properly operating memory cell (hereafter referred to as a “pass cell”) or fail cell. Unfortunately, sequentially testing millions (or billions) of individual memory cells requires a great deal of time, but practical commercial considerations demand high testing productivity at relatively low cost. Therefore, as contemporary semiconductor memory devices increase in integration density, it is important to maximize the efficiency of applied test procedures.
Semiconductor testing is accomplished using a variety of apparatuses and methods. Many of these apparatuses and methods have been developed to improve testing efficiency. As a general rule, most test apparatuses and methods applied to semiconductor memory devices use some form of parallel bit testing (i.e., test signals and/or test data are applied to more than one memory cell simultaneously).
Many parallel test methods applied to memory cells use well known logic circuits, such as the exclusive OR (XOR) or exclusive NOR (XNOR). During parallel test procedures, “like data” (i.e., logically identical data values) is written to a plurality of memory cells, and then a logic operation is performed using an XOR or XNOR logic circuit when reading the stored data from the plurality of memory cells. When like data is read, a pass cell condition is determined for the memory cells being tested. However, when different data is read, a fail cell condition is determined. By effectively testing multiple memory cells in a single logic operation, overall test time is reduced.
Recent commercial demands have motivated the development of non-volatile memory devices that enjoy high performance and low power consumption. Such non-volatile memory devices do not require the refresh operation most commonly associated with conventional DRAM. One example of next generational memory devices is the so-called phase-change random access memory (PRAM). The PRAM uses a phase-change material of variable resistance to store data.
Phase-change materials currently used to implement PRAMs include certain chalcogenides that are characterized by a resistance that changes with material state under the influence of temperature. One commonly used phase-change material is GexSbyTez (hereinafter, referred to as “GST”) which is an alloy of germanium (Ge), antimony (Sb) and tellurium (Te).
These types of phase-change materials have multiple material states (e.g., crystalline and amorphous) that may be quickly switched between by application of a defined temperature or temperature range over time. The desired phase changing temperature may be applied to the phase-change material forming PRAM using the joule heating effect of an applied electrical current.
In the description that follows, it is assumed that a phase-change material implementing a PRAM is characterized by a relatively high resistance in an amorphous state and a relatively low resistance in a crystalline state. It is further assumed that the amorphous state of the phase-change material corresponds to a reset data value (or a logical ‘1’ value) and the crystalline state corresponds to a set data value (or a logical ‘0’ value).
An exemplary write operation for a PRAM device will now be described under these working assumptions.
To write a reset data value of ‘1’ (hereafter, a ‘1’) in a specific memory cell, current is passed through the constituent phase-change material. After the phase-change material is heated to its melting point or above, it is rapidly cooled. This application of joule heating places the phase-change material in the amorphous state and stores a ‘1’. The amorphous state is thus referred to as the reset data state.
To write a ‘0’ in a specific memory cell, a current is passed through the constituent phase-change material. After the phase-change material is heated to its crystallization temperature or above, it is maintained for a predetermined period of time and is then cooled relatively slowly. This application of joule heating places the phase-change material in the crystalline state and stores a ‘0’. The crystalline state is referred to as the set data state.
During a read operation, a specific memory cell is first selected by the conventional application of control voltages to corresponding word and bit lines. An externally applied current is then passed through the selected memory cell. A data value of ‘1’ or ‘0’ is sensed in relation to a difference in voltage change resulting from the current resistance state of the phase-change material.
The testing of high density PRAM devices presents many of the same challenges associated with other types of semiconductor memory devices. It is necessary to apply test methods that reduce power consumption and testing time while also reliability testing each and every memory cell in the PRAM memory cell array. However, the differences between write and read operations applied to PRAM as compared with other forms of memory, such as DRAM must be considered in the development of effective test methods.